Some error-correcting algorithms, such as Low-Density Parity-Check code (“LDPC code”), permit higher data transmission rates than many other algorithms used today. LDPC code may even permit data transmission rates at close to the theoretical maximum, called the “Shannon Limit.”
LDPC code, however, uses sets of parameters to perform its error correcting (e.g., Log Likelihood Ratio (“LLR”) parameters). These sets of parameters are typically stored in separate sets of memory, either on a single, integrated chip or on separate chips. In either case, these sets of parameters may be read from and written to these sets of memory by a computational unit that performs the LDPC code's algorithm using a cache (e.g., a Static Random Access Memory, or SRAM).
To read and write these parameters to and from these sets of memory, current systems often use high-speed buses and high-speed transmission lines. These high-speed buses and high-speed transmission lines—even though they may be very fast—still slow the process of error correcting. This reduces the advantages of the LDPC code's algorithm because the computational unit and/or its cache has to wait on the buses and transmission lines to transmit the data.